I have simply completely lost interest in FPGA design because of AI. I'm not here to argue about AI. I dont care if you love it or hate it. I personally simply have no interest in being in a position where the code for my designs is auto generated. Converting ny designs into RTL was my favorite part about the field, and the only reason I care to tolerate the other associated BS. And I'm already watching it get tossed out the window.
I'm curious what others think someone like me could find satisfaction from professionally.
I’ve reached the assessment centre for the Electronics Industrial Placement at Mercedes-AMG PETRONAS F1 in Brackley. I’m a second-year EEE student interested in FPGA/RTL design, with personal projects in SystemVerilog.
Does anyone know if F1 electronics team do sky FPGA/RTL work, or is it mainly PCB design, embedded systems and testing?
Having just completed Verilog, I want to start learning System Verilog, but couldn't find any comprehensive resources online, that can teach complete SV right from scratch.
Also, to the experienced people here, I wanna ask if I want to build my profile in RTL Design and Verification, will doing Verilog and System Verilog be enough, or shall I work on something more? (considering today's industry standards
I have an older Basys 3 board that I want to mess around with and the tool chain looks like it needs to install 28GB on my drive. IS there a less bulky installation I can do to support this board?
I have implemented a simple SPI master peripheral in an FPGA with the following characteristics:
SCLK clock is peripheral clock (CLK) divided by 4. Specifically SCLK = 25MHz and CLK = 100MHz.
Only outputs data. I.e. Only MOSI implemented.
SPI Mode 0. I.e. MOSI changes on falling edge of SCLK and is latched on the rising edge of SCLK.
All logic clocked by the rising edge of CLK.
I have created the necessary clocks using create_clock and create_generated_clock to specify CLK and SCLK. I have also added min and max output_delay constraints of -TSCLK/4 (= -10ns) and TSCLK/4 (= 10ns) respectively, which is sufficient (given the maximum skew on the PCB) to meet the setup and hold requirements of the connected devices. The confusing part is what the correct multicycle exceptions are for setup and hold. Without exceptions the timing analysis fails both setup and hold.
What appears to be correct to me from looking at the waveforms in the timing analyser is for the setup and hold multicycle exceptions to be:
The setup exception adds an additional clk period for setup (i.e. from 10ns to 20ns), but also shifts the hold by 1 clk period (i.e from 0ns to 10ns). The hold exception pulls the hold requirement back by 3 clk periods (i.e. from 10ns to -20ns).
More generally, it seems the correct multicycle exceptions for SPI using a divided down clock to generate SCLK should be:
Where clk_div is the divider used to generate SCLK from CLK.
Note that the hold multicycle exception is greater than the setup multicycle exception. The timing analyser does not complain about this, but the synthesis tool spews out a message that it is ignoring the hold multicycle exception because it is larger than the setup multicycle exception.
Am I missing something? Are the exceptions wrong? Are different exceptions required for synthesis and timing analysis? If so, what are the correct timing constraints for synthesis of this extremely simple output-only SPI interface? The two examples I could find on the web for constraining SPI using a divided-down clock for SCLK also have a hold multicycle exception greater than the setup multicycle exception that match mine.
Given that SPI is such a common protocol and dividing down a high-speed clock to generate SCLK is a very common way to implement it, I am surprised there are so few examples of what the correct timing constraints are.
I’ve been thinking about how much of DMA correctness actually lives in the HW/SW contract rather than in the data mover itself.
On the Zynq UltraScale+ setup I’m working with, descriptor retirement is based on hardware HEAD rather than treating IRQ count as completion authority. Linux maintains monotonic producer/clean indices, while the FPGA handles the descriptor ring, AXI DDR traffic, completion/error IRQs and performance counters.
The current run shown here is at 2,048 completed descriptors with prod/clean/head all aligned, 131,072 bytes accounted for and no DMA error state.
One interesting result was that 2,048 completions did not necessarily mean 2,048 Linux IRQ-handler entries because completion causes can coalesce. That reinforced why IRQ count should be treated as notification, not as the authoritative completion count.
Curious how others structure that contract in custom DMA or accelerator drivers.
I’ve just started learning it to strengthen my verification skills and pass interviews. (I’m a recent graduate).
I absolutely hate it, It just seems overly convoluted for no reason.
If anyone can point to resources that keep things simple and isn’t confusing I’d really appreciate it
I'm using the KR260, and I'm wondering whether anyone has encountered similar issues.
My software running on the R5 communicates with AXI Ethernet Lite to access the PHY in the PL, but when I scan the MDIO bus, I only read zeros and cannot detect any PHY.
I've also tried using an explicit IOBUF rather than relying on the one instantiated by the Ethernet Lite core, but the issue persists.
I'm struggling to identify what could be wrong because, at least theoretically, the architecture and configuration seem correct.
If anyone has encountered a similar issue or has suggestions on what to check, I'd really appreciate the help. I can provide more details about the architecture, Vivado configuration, MDIO implementation, and R5 software if needed.
I've been debugging this for a while, and it's getting pretty frustrating because nothing obvious seems to be wrong.~
I'm also attaching the simple R5 fw i did just for testing the MDIO (it seems like after the stream of '1' it writes "01" instead of "10" for read)
Also showing the wiring of the MDIO from Axi Ethernet Lite, to my mii2rgmii and to the output
Like it seems when T = 0 , it MDIO oscillates so its writing what we expect ( even though not correctly i guess ), but when it goes back to T = '1' so we are in high impedance mode reading the bus is just high, so PHY isnt responding, meanwhile the PHY rxc is fine he produces it so the phy is alive i believe
I'm looking to sell my brother's ALINX AXU4EV-P FPGA development board he passed away few months ago and I found this box in his stuff I'm trying to find someone who can put his equipment to good use rather than have it sitting unused
I'm not really into FPGAs I'm more of a PC Guy with occasional Arduino and Pi projects homelab ect FPGAs are just black magic to me really hard to understand even he wasn't able to explain it to me
I don't know how much this board is going for nowdays I remember he bought it for 950$ ish in early 2024 I'm guessing the price has dropped hard since then, so I'd appreciate some advice on its current value
If you're interested please contact me through email "abodyaeabod@gmail.com" or here on Reddit
Currently building a project that maps a digit onto an 8x8 grid and determines whether a cell containing traces is lit or not, '1' or '0' / HIGH vs. LOW. Then, it tries to predict the digit using the placement of those 64 1s and 0s and multiplying it with the weight of that specific cell and its positive, zero, or negative contribution towards the "score" of that number.
The weights are sent over a COM port with pyserial and then go through a USB-UART to FPGA pins. The FPGA adds a weight or a zero (`x[i] ? w[i] : 0` in `score.sv`). Then, a tree of adders works to compute the score and send it back over to software over tx/rx with UART. The FPGA works at 50 MHz as currently planned, so each bit is 434 cycles at 8.68 microseconds.
Was wondering if anybody could review the diagrams or code or reach out if they're interested in some work on the embedded systems programming in the middle of the software/hardware side. Also, what would the practicality of being able to deploy the model onto an MCU with an OLED display and a camera with real-time predictions be? For example, using a camera to read the digit and then running the code on the MCU and predicting the digit in real-time and displaying that. I think that would be pretty cool, but I'm a second year uni student and still learning a lot more. Working with my friend on this right now.
Here is the warning message generated. The bit gets programmed but minus the ILA logic. The design is pretty small, so I am guessing ILA's cant be causing this error.
WARNING: [Labtools 27-3361] The debug hub core was not detected.
Resolution:
Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active.
Make sure the BSCAN_SWITCH_USER_MASK device property in Vivado Hardware Manager reflects the user scan chain setting in the design and refresh the device. To determine the user scan chain setting in the design, open the implemented design and use 'get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]'.
For more details on setting the scan chain property, consult the Vivado Debug and Programming User Guide (UG908).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.
I checked in the implemented design and ILA Logic and dbg_hub core is present and related clocks are connected to it.
Hi. I am developing my 16 bit microcontroler in systemverilog. Today i got my tang nano 9k and my processor is already computing pi. Am I on good path?
I'm trying to implement different machine learning models on AMD Versal boards, and I'd like to explore different implementation approaches.
In particular, I'm interested in:
Deploying ML models using Vitis AI.
Exploring the use of AI Engines (AIE).
Optimizing neural networks for DPU-based inference.
Understanding how to map different parts of a model to the AI Engines and programmable logic.
I've found some documentation, but I'm struggling to find a structured learning path that covers these topics in practice.
Could you recommend any books, tutorials, example projects, or documentation?
What would be a good step-by-step learning plan for someone who wants to understand both the software workflow and the hardware implementation?
Any advice or resources would be greatly appreciated. Thanks!
Hey folks! Looking for a freelance FPGA engineer who has experience with Xilinx Kintex UltraScale, high-speed ADCs, PCIe, and NVIDIA Jetson AGX Orin for a custom hardware development project.
If you have relevant experience or know someone who does, please DM me!
I’m a second-year EEE student in the UK applying for RTL/FPGA internships and placements: Graphcore (silicon), Arm, AMD, Riverlane, Apple (GPU RTL), EnSilica, Cirrus Logic, Allegro, BAE and others.
My background is mainly SystemVerilog (UART, async FIFO with CDC, FPGA projects on a Basys 3). I’m comfortable in Python and my C is basic.
For anyone who’s interviewed or has experience at these or similar companies:
Was Python or C actually tested in interviews, or was it mostly digital design?
If coding came up, what level was it (scripting, data structures, LeetCode-style)?
Is basic C worth prioritising, or is Python enough?
Hey, I’m not sure if this is the right area to post this (if not please let me know where) but I recently did a hackerrank interview for an fpga engineer for virtu and was wondering the response time? It’s been just over a week now and haven’t heard back?
Hello everyone, I’m a 24-year-old Electrical Engineering graduate in Canada (from a tier 1 school). I was wondering if anyone on this subreddit could give me some advice on how to fix the situation I’m in right now.
Basically, I graduated 2 years ago without any internships. Now, don’t get me wrong, I was a very hard-working student. I actually spent a great deal of time going to career fairs, using my university’s career resources to help with my resume, and participating in a software development club. I excelled in my courses, and I even ended up getting interviews at AMD, Synopsys, The Six Semiconductor, and so on. The issue was, my mental health tanked really hard in my third year, and it wasn’t just depression or anxiety. I was dealing with panic disorder and severe psychosis (it’s a long personal story, and I don’t want to get into it). Anyone who’s had panic disorder knows it’s literal hell on earth. My mental health issues basically caused me to miss every interview I was offered, so I didn’t land any internships in my third year. It’s a miracle I even managed to pass my classes that year. Unfortunately, because of how terribly I did, my GPA dropped from a 3.9 to around a 3.5.
Fast-forward to my fourth year. I was planning on extending my degree and doing 2 years worth of internships before graduating, but due to money problems, I was forced to find whatever work I could. So I started doing full-time contract work in the data space while also being a full-time student. I was actually getting paid more than most interns in Canada, so I decided to stick with the contract job. After graduating with my bachelor’s, I got hired to do data engineering work at an AI company, and a year later, I was promoted to product manager.
The issue is, I really don’t like my work, as it doesn’t have anything to do with Electrical Engineering. And to be honest, although the salary is pretty good, I know I can do much better.
Now, I want to pivot to the ASIC/VLSI/FPGA/silicon/digital design space, since I’ve always been interested in it. I’m aiming to land roles at companies such as Qualcomm, Intel, Nvidia, AMD, Synopsys, Marvell, The Six Semiconductor, and TI. The problem is, I don’t have any experience in these areas. I’ve come up with a few ideas for how to make the switch, and I’d really appreciate any help/guidance.
I was thinking of doing a master’s in microelectronics/computer engineering at UofT/Waterloo/McMaster (or any other reputable school), but I’m not sure which type of master’s to do. There are thesis-based and course-based master’s programs. A thesis-based master’s lets you do research and provides funding, but you don’t get to do an internship. A course-based master’s lets you do up to 1 year of internships, but since there’s no research component, you lose the option of doing a PhD in the future (although you do get to work on a capstone project). The thing is, I’ve seen a lot of internship postings that specifically ask for students pursuing a bachelor’s degree (not a master’s). So I feel like there’s no point in even doing a master’s, since the only reason I’d do one is to get an internship (I can learn the course material on my own). I was also thinking of working full-time at my company while doing the master’s part-time.
My other idea is to do a 2nd bachelor’s degree in computer engineering. Maybe I could transfer credits and finish it in 1 year? That would let me do internships as a bachelor’s student (up to 2 years worth), but I haven’t researched this idea yet, and I don’t even know if it’s possible to transfer credits. I also feel like I’d just be relearning what I’ve already learned.
Or maybe I should skip the master’s and spend the next year working on projects and self-learning? (But if I’m going to be learning on my own anyway, I might as well do a master’s and at least get a degree out of it.)
I don’t even know if I can get into a thesis-based master’s, since my third year tanked my GPA to a 3.5, which isn’t competitive. I also don’t have any previous research experience, except for my product management job, which involves reading a lot of research papers and implementing ideas from the research papers.
I just don’t know where to go from here, and I’m a bit lost. I’m grateful to have a good job in this economy, but this isn’t what I want to do. I want to pivot back to what I love.
I'm using the KR260, and I'm wondering whether anyone has encountered similar issues.
My software running on the R5 communicates with AXI Ethernet Lite to access the PHY in the PL, but when I scan the MDIO bus, I only read zeros and cannot detect any PHY.
I've also tried using an explicit IOBUF rather than relying on the one instantiated by the Ethernet Lite core, but the issue persists.
I'm struggling to identify what could be wrong because, at least theoretically, the architecture and configuration seem correct.
If anyone has encountered a similar issue or has suggestions on what to check, I'd really appreciate the help. I can provide more details about the architecture, Vivado configuration, MDIO implementation, and R5 software if needed.
I've been debugging this for a while, and it's getting pretty frustrating because nothing obvious seems to be wrong.
Sigasi Visual HDL 2026.5 is out, and the Sigasi MCP server works with your agent in VS Code (and Cursor): Claude Code, OpenAI Codex, Mistral Vibe, and others.
Your agent can read in real-time Sigasi's linting violations, explore the structure of your project, and format HDL, through the same project model you see in the editor.
Sigasi MCP Server is not a separate product. It is built into Sigasi Visual HDL and included in every edition, so there is no second license to buy and no second tool to keep in sync. The engineer in the editor and the agent calling MCP work against one model of the design.
Also in 2026.5:
WaveDrom timing diagrams rendered from your HDL comments, in hovers and generated documentation
Spell checking for comments and strings in SystemVerilog, Verilog, and VHDL
A project-level dependency search path, so a Modular Project works on every checkout
The agent writes the HDL. Sigasi checks it against the real project. You decide what moves forward.
